Aviation Parts XQV300-4BG352N Xilinx FPGA Package PLASTIC, BGA-352
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xPackage | PLASTIC, BGA-352 | Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
---|---|---|---|
Combinatorial Delay Of A CLB-Max | 0.8 Ns | JESD-30 Code | S-PBGA-B352 |
Operating Temperature-Min | -55.0 Cel | Supply Voltage-Nom | 2.5 V |
Supply Voltage-Max | 2.625 V | Technology | CMOS |
Terminal Finish | Tin/Lead (Sn63Pb37) | Time@Peak Reflow Temperature-Max (s) | 30 |
Aviation Parts XQV300-4BG352N Xilinx FPGA Package PLASTIC, BGA-352
Descriptions of Aviation Parts :
The QProTM VirtexTM FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 0.22 µm CMOS process. These advances make QPro Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex family comprises the four members shown in Table 1. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the QPro Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market. Refer to the "VirtexTM 2.5V Field Programmable Gate Arrays" commercial data sheet for more information on device architecture and timing specifications.
Features of Aviation Parts:
Certified to MIL-PRF-38535 (Qualified Manufacturer Listing) Guaranteed over the full military temperature range to +125°C) Ceramic and Plastic Packages Fast, high-density Field-Programmable Gate Arrays Densities from to 1M system gates System performance to 200 MHz Hot-swappable for Compact PCI 16 high-performance interface standards Connects directly to ZBTRAM devices Four dedicated delay-locked loops (DLLs) for advanced clock control Four primary low-skew global clock distribution nets, plus 24 secondary global nets LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register Configurable synchronous dual-ported 4K-bit RAMs Fast interfaces to external high-performance RAMs Dedicated carry logic for high-speed arithmetic Dedicated multiplier support Cascade chain for wide-input functions Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset Internal 3-state bussing IEEE 1149.1 boundary-scan logic Die-temperature sensing device
Specification of Aviation Parts :
Mfr Package Description |
PLASTIC, BGA-352 |
REACH Compliant | Yes |
Status | Discontinued |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
Combinatorial Delay of a CLB-Max | 0.8 ns |
JESD-30 Code | S-PBGA-B352 |
JESD-609 Code | e0 |
Moisture Sensitivity Level | 3 |
Number of CLBs | 1536.0 |
Number of Equivalent Gates | 322970.0 |
Number of Inputs | 260.0 |
Number of Logic Cells | 6912.0 |
Number of Outputs | 260.0 |
Number of Terminals | 352 |
Operating Temperature-Min | -55.0 Cel |
Operating Temperature-Max | 125.0 Cel |
Organization | 1536 CLBS, 322970 GATES |
Package Body Material | PLASTIC/EPOXY |
Package Code | LBGA |
Package Equivalence Code | BGA352,26X26,50 |
Package Shape | SQUARE |
Package Style | GRID ARRAY, LOW PROFILE |
Peak Reflow Temperature (Cel) | 225 |
Power Supplies | 1.2/3.6,2.5 |
Qualification Status | Not Qualified |
Screening Level | 38535Q/M;38534H;883B |
Seated Height-Max | 1.7 mm |
Sub Category | Field Programmable Gate Arrays |
Supply Voltage-Nom | 2.5 V |
Supply Voltage-Min | 2.375 V |
Supply Voltage-Max | 2.625 V |
Surface Mount | YES |
Technology | CMOS |
Temperature Grade | MILITARY |
Terminal Finish | Tin/Lead (Sn63Pb37) |
Terminal Form | BALL |
Terminal Pitch | 1.27 mm |
Terminal Position | BOTTOM |
Time@Peak Reflow Temperature-Max (s) | 30 |
Length | 35.0 mm |
Width | 35.0 mm |